1. Technical Field
Methods and apparatuses consistent with exemplary embodiments relate generally to semiconductor circuit designs, more particularly, to estimating yields of integrated circuits and optimizing designs for the integrated circuits.
2. Description of the Related Art
In designing an integrated circuit, such as a system-on-chip (SoC), static timing analysis (STA) is performed to analyze timings of the designed integrated circuit. The static timing analysis may reflect process variations in designing the integrated circuit, thereby improving a yield of the integrated circuit. For example, the static timing analysis may calculate a slack of each timing path included in the integrated circuit to determine whether there is a timing failure at the timing path, and thus a designer of the integrated circuit may correct or modify the design for the integrated circuit based on the calculated slack. However, since the slack calculated by the static timing analysis cannot represent probability information about timing pass or fail, it is difficult to estimate the yield of the integrated circuit based on the slack.